M4 HPSC Research
Objective
Establish what PIC64-HPSC, the next-generation RISC-V research target - can contribute: measurable hardware partitioning / virtualization feasibility, not a production claim.
Scope
Start:
HPSC
├── RTEMS baseline
├── WorldGuard experiments
└── Xen feasibility
Then investigate:
Xen
↓
RISC-V guest
↓
RTEMS guest
Xen-on-HPSC is not a prerequisite for the architecture: x86-64 and NG-ULTRA stand independently; HPSC is what makes “portable” a three-point comparison rather than a two-point one.
Deliverables
RTEMS-on-HPSC baseline (recorded)
WorldGuard partitioning experiments (which resource classes are partitioned: cores, cache, interconnect, peripherals, memory)
Xen feasibility findings on RISC-V guest infrastructure (host bring-up, domain creation, virtual timer, interrupts, memory)
feasibility report: what HPSC can/cannot provide for the contract semantics (feeds RP1’s “which semantics are hardware-specific” column)
Tests / acceptance gate
HPSC demonstrates measurable hardware partitioning / virtualization feasibility.
“Measurable” is the keyword: numbers (or a documented inability to measure a given channel), not capability adjectives. Xen RISC-V guest support remains an active upstream development area, so interpretation of each sub-finding carries its own status label.
Current status
Planned / research track (start after M2, or in parallel where
personnel allow, the plan default is after M1/M2 baselines exist so the
comparison partitions are already real).
Known limitations
No production claim: M4 does not make HPSC a “supported platform” - it stays a
Researchtarget in the platform matrix.WorldGuard behavior is documented at the level of what experiments actually demonstrated; the vendor’s architectural marketing claims (e.g., “end-to-end spatial partitioning”) are not GoMyRobotOS claims.
The system-controller processor (candidate for independent monitoring / fault management, cf. GoMyRobotGuard) is investigated under the Xen feasibility work, not as a Guard implementation.